CSCI3121 - Computer Organization - Summer 2013

Final Exam

• Outline of marking scheme, pre-requisit etc..

Assignments

• Assignment 1 - released May 14; due May 23 email submission (text or pdf) before end of day or hand in during lecture.
• Assignment 2 - due TBA, email submission or hand in during lecture.
  • Blank Pipeline timing diagrams
• Assignment 3 - due TBA, email submission or hand in during lecture.
• Assignment 4 - due TBA, email submission or hand in during lecture.
  • Timing diagrams
• Assignment 5 - due TBA, email submission or hand in during lecture.

Presentations

• Presentation groups
• Group #1 - Presenting July 16nd
• Group #2 - Presenting July 16nd
• Group #3 - Presenting July 18th
• Group #4 - Presenting July 18th

Benchmarking

• Benchmarking Slides
  • Current clock power dissipation trends
  • Current CPU socket trends
• Case Study - Notes on SPEC CPU2000 comparison between ALPHA architectures.
• Case Study Appendix
  • Spec benchmark site
• CPI example

Instruction Set Architectures

• ISA Profiling

Instruction Level Parallelizm: An introduction

• Basic 5-stage ILP
• Data Hazards
• Control hazards
• Multi-cycle pipe
  • Pipe timing diagram for question
• Summary of basic instruction level pipe
• Branch Target Buffers and Control Hazards
  • Solution for BTB example question
• Dynamic Scheduling in hardware
  • Timing diagram and Resourvation Station operation
  • Conclusion
• Multi-issue or Superscalar architecture: reducing CPI below unity
  • Timing diagrams
• Speculative Execution
  • Timeing diagrams
• Thread-Level Parallelism

Memory Hierarchy

• Basic Memory Hierarhcy
• Miss Rate Reduction
• Miss Penalty and Hit Rate
• Virtual Memory

Thread-level Parallelism and Cache coherence

• Shared-memory architectures
• Synchronization
• Memory consistency models

Case Studies

• Pentium CPU
• General purpose GPU computing